Generally, the invention relates to a switch system in which circuit switching is performed in a distributed time switch in which time switching units are located in switch ports connected to a time shared medium in a switch core.
More particularly, the present invention relates to a digital time switch system which includes a switch core and a number of switch ports and is intended to be used in a telecommunication network, in which the switch ports share the bandwidth of a bus by time-division multiplexing, on which the time is divided into time slots which are assembled in frames, data transmission between the switch ports is performed in time slots which have been assigned to a respective switch port by a superior control means so as to avoid bus conflict, and each switch port has access to the whole bandwidth of the bus and by means of the superior control means selects the data which is intended for the switch port.
In switch systems wherein the switch core consists of a common time shared medium the switch core can be very simple. In known systems of this kind the switch core often consists of only a passive bus.
One advantage of switch systems of this type is that the costs of the switch core become low, whereby higher cost modularity can be attained for scaleable systems. Since the switch core constitutes a fixed basic cost for a system, the total cost for small systems can be lower when the cost of the switch core is low, whereby the cost efficiency becomes better for these small systems.
A passive bus can, however, suffer from several problems. One problem is that erroneously appearing switch ports can disturb the function of the bus by driving it at points of time which have been assigned to other switch ports. This can result in bus conflict.
Another problem is the high frequency properties of the bus. More particularly, at high frequencies impedance adaption is required, since the bus then has the character of a transmission line. For different reasons the bus is, however, difficult to impedance match, and therefore the bandwidth is thus in reality strongly limited.
A further problem that can appear in connection with a passive bus is related to error detection. It is difficult to identify a disturbing switch port since several potentially erroneous switch ports can drive common electrical nodes, i.e. the node or nodes of which the bus consists.
U.S. Pat. No. 5,153,455 describes a digital communication system wherein a plurality of IC circuits can communicate with each other via a common bus. The communication from the circuits to the bus is performed by means of an OR function admitting that an arbitrary circuit can communicate with all other circuits.
From U.S. Pat. No. 5,086,427 a system appears wherein a plurality of terminals communicate through drive units via a common system bus. The drive units are each controlled by individual logical control units in the form of AND gates. By making the control signal to a drive unit assume the logical value 0 during a time period in which the unit is not allowed to use the bus, it is avoided that more units use the bus simultaneously. More particularly, this is attained by the output of a clock controlled flipflop forming one of the inputs of the logical control unit.
U.S. Pat. No. 4,656,471 describes a system for connecting a user to a bus without the bus becoming blocked in case of an error, if any, in the user terminal. The terminal is put into contact with the bus via a switch which is conducting if a control signal connected thereto indicates that the terminal operates as it should. Otherwise the switch breaks.
U.S. Pat. No. 4,613,858 relates to a method for decreasing the risk for bus error due to terminal errors. This is attained by the drive circuit of the terminal being controlled by an output signal from an AND gate the inputs of which are connected to two control signals. The two control signals which define the time interval in which the terminal may send, are generated internally and externally which makes that an internal error does not affect the sending time.
EP 396,119 describes a method for multiplexing broad band signals by means of a plurality of logical elements such as NAND gates. From a number of input signals the desired input signal is selected by giving to the undesirable signals the logical value 0 by successive NAND operations.
U.S. Pat. No. 5,151,896 discloses a distributed digital telephone system wherein each switch port contains switch and control functions. The switch ports are connected to TDM buses. In case of an error there is a possibility to disconnect the part of the system being faulty, without affecting the rest of the system.